Nano Devices and Processing Lab

Seungjae Kim

● Course: M.S. Course, 2 year

● Biography: M.S. Graduate School of Semiconductor Technology, Pohang University of Science and Technology (Sep. 2024 - )

 B.S. Electrical Engineering, Chung-Ang University (Mar. 2018 - Aug. 2024)

● Research interests: V-NAND

● E-mail: sjkim0421@postech.ac.kr

● Publications

International Journals

1. Donghyun Go, Jounghun Park, Donghwi Kim, Jinuk Ju, Seungjae Kim, Jungsik Kim, and Jeong-Soo Lee, "Hole Trap Extraction in Charge Trap Layer of 3D NAND Flash Memory", IEEE Transactions on Electron Devices, vol 73, no. 2 (2026)

International Conferences

Domestic Conferences

1. 김승재, 고동현, 김동휘, 원대한, 이정수 "Spatial Trap Profiles in the Charge Trap Layer of 3-D NAND Flash Cell using a Positive-Bias Induced Trap Extraction (P-BITE) Method", 한국반도체학술대회 (KCS 2026)

2. 원대한, 고동현, 김동휘, 김승재, 김현준, 이정수, "Asymmetry-Based Identification of Grain-Boundary Position and Its Impact on Device Variability in 3-D NAND Flash Memory", 한국반도체학술대회 (KCS 2026)

Patents

● Awards