Nano Devices and Processing Lab
Jaeyong Choi
● Course: Integrated course, 2 year
● Biography: Ph. D. Electrical Engineering, Pohang University of Science and Technology (Mar. 2023 - )
B.S. Electrical Engineering, Hongik University (Mar. 2016 - Feb. 2023)
● Research interests:
● E-mail: jychoieee@postech.ac.kr
● Publications
International Journals
Iksoo Park, Jaeyong Choi, Jungsik Kim, Byoung Don Kong, and Jeong-Soo Lee, "Effect of Quasi-One-Dimensional Properties on Source/Drain Contacts in Vertical Nanowire Field-Effect Transistors (VNWFETs)", Micromachines, vol 15, no. 4, p. 481
International Conferences
Domestic Conferences
김종우, 윤길상, 고동현, 박정훈, 김동휘, 안욱주, 최재용, 이정수, "Improving Retention Characteristics in 3D NAND Flash Memory by Re-Program with Counter-Pulse", 반도체공학회 하계학술대회 (ISE 2023 Summer)
Patents
● Awards